1. Field of the Invention:
The present invention relates to a semiconductor memory device, and more particularly to a page-mode read circuit used in a semiconductor memory device having a page mode.
2. Description of the Related Art:
Recently, as the operation speed of microprocessors and the like is increased, semiconductor memory devices are increasingly required to operate at higher speeds. Accordingly, there has been developed a semiconductor memory device having a normal mode in which the random access is rapidly performed, and also having a page mode in which the access method is somewhat limited, but the read operation can be performed at a higher speed.
The read operation in the page mode is described. A plurality of memory cells in a memory cell array are simultaneously selected in accordance with a column address and a row address of an input address, and a plurality of data units are read and fed up to a sense amplifier as page data. In such a state, a page-mode address is changed, so that the data units stored in the selected plurality of memory cells are rapidly switched and sequentially output.
FIG. 8 is a block diagram which illustrates a general configuration for performing a page-mode operation in a conventional mask read-only memory (ROM). FIG. 9 is a diagram showing a specific circuit configuration of components which contribute to the page-mode operation of the mask ROM. FIG. 10 is a timing chart illustrating an exemplary read operation in the page mode.
Herein, address signals A0 to A2 among address signals A0 to A19 indicate a page-mode address. The address signals A3 to A6 indicate a column address, and the address signals A7 to A19 indicate a row address.
As shown in FIG. 8, a conventional mask ROM 200 having a page mode includes a memory cell array 10 in which memory cells are arranged in a matrix. The mask ROM 200 further includes a row selection section for selecting memory cells arranged in a row corresponding to the row address indicated by the address signals A7 to A19. The row selection section includes an input buffer 11 for receiving the address signals A7 to A19, a predecoder A 12 connected to the output of the input buffer 11, and an X decoder 13 for selecting a row of the memory cell array 10 in accordance with the output of the predecoder A 12.
The mask ROM 200 also includes a column selection section for selecting a plurality of columns of memory cells corresponding to the column address indicated by the address signals A3 to A6 of the column address. The column selection section includes an input buffer 21 for receiving the address signals A3 to A6, a predecoder B 22 connected to the input buffer 21, and a Y decoder/selector 23 for selecting a plurality of columns of memory cells of the memory cell array 10 in accordance with the outputs CA0 to CA3 and CB0 to CB3 of the predecoder B 22. The Y decoder/selector 23 includes a Y selector 23b for selecting each column of the memory cell array 10, and a Y decoder 23a for allowing the Y selector 23b to simultaneously select predetermined columns, as shown in FIG. 9.
The Y decoder/selector 23 is connected to a sense amplifier group 24 including a plurality of sense amplifiers for sensing respective information stored in the memory cells. The output of the sense amplifier group 24 is connected to a selector 33 for selecting the output from the respective amplifiers in accordance with sense amplifier selection signals P0 to P7 based on the address signals A0 to A2 of the page-mode address.
The selector 33 is connected to a page-mode decoder 32 which outputs the sense amplifier selection signals P0 to P7. The input of the page-mode decoder 32 is connected to an input buffer 31 which receives the address signals A0 to A2 of the page-mode address. An output circuit 20 outputs the output of the selector 33 to an output terminal 2.
Next, the operation is described with reference to FIGS. 9 and 10.
At time t0, the input of the address signals A0 to A19 is made valid. In this case, the mask ROM is set in a normal random access mode.
First, the address signals A7 to A19 of the row address are decoded by the input buffer 11, the predecoder A 12, and the X decoder 13, so that any one of word lines WLi is made active. Herein, the level of the active word line is "High."
At this time, based on the address signals A3 to A6 of the column address, one of the output signals CA0 to CA3 and one of the output signals CB0 to CB3 of the predecoder B 22 are made active (i.e., set in the "High" level).
For example, when the address signals A3 to A19 specify the address a, the output signals CA0 and CB0 are made active. Accordingly, only output signal CS0 among output signals CS0 to CS15 of the Y decoder 23a is made active (i.e., "High"), so that a column selection MOS transistor 3 of the Y selector 23b, which receives the output signal CS0 from the Y decoder 23a as its input, is turned "ON." In this way, memory cells M0.sub.i0, . . . , M0.sub.i7 are selected. The respective information of the selected memory cells is transmitted to common bit lines CBIT0 to CBIT7 via the column selection MOS transistors 3, and then input into the sense amplifier group 24. At time t1, the outputs SA0 to SA7 of the sense amplifiers are made valid, so that the data read of the page at the address a specified by the address signals A3 to A19 is completed.
In accordance with the address signals A0 to A2 of the page-mode address, only one of the output signals P0 to P7 of the page-mode decoder 32 is made active (i.e., set in the "High" level), so that one of the sense amplifier outputs SA0 to SA7 is selected by the selector 33. The selected sense amplifier output is output to the output terminal 2 through the output circuit 20 at time t2.
Thereafter, at time t3, the change of the address signals A0 to A2 of the page-mode address is started, the selector 33 sequentially selects the data of the sense amplifier outputs SA0 to SA7, and the selected data is output to the output terminal 2 through the output circuit 20. The response at the output terminal 2 to the start of the change of the address signals A0 to A2 appears at time t4. As described above, the device is set in the page mode in which the high-speed read can be performed from the start of the change of the address signals A0 to A2. The time period for reading is (t4-t3).
For example, when the address signals A3 to A19 specify an address (a+1) corresponding to the next page at time t6, the predecode output signal CA0 is made inactive (i.e., "Low"), and the predecode output signal CA1 is made active (i.e., "High"). Accordingly, the Y-decode output CS0 is made inactive (i.e., "Low"), and the Y-decode output CS1 is made active (i.e., "High"), so that the memory cell M1.sub.i0, . . . , M1.sub.i7 are selected. The respective information of the memory cells is transmitted to the common bit lines CBIT0 to CBIT7 via the column selection MOS transistors 3, and then input into the sense amplifier group 24. As described above, when the page data is changed, the read of the information from memory cells is performed in the normal random access mode, and the high-speed read cannot be performed.
As disclosed in Japanese Laid-Open Patent Publication No. 5-144255, there has been already developed a semiconductor memory device having a page mode in which the high-speed read can be performed when the page data is changed in order to successively read the page data. FIG. 11 is a block diagram showing a configuration of a semiconductor memory device described in the above-identified publication. FIG. 12 is a timing chart for illustrating the operation of the semiconductor memory device illustrated in FIG. 11.
In FIG. 11, a latch circuit 14 latches page data output from the sense amplifier group 24. The latch circuit 14 performs the latch operation in accordance with an output (a .phi.LATCH signal) of an address change detector 19 for detecting the change of address signals. The output of the latch circuit 14 is transmitted to the selector 33. An output buffer 17 outputs the selection signal of the selector 33 to an output terminal 18, which corresponds to the output circuit 20 shown in FIG. 8. The other components are identical to those in the mask ROM shown in FIGS. 8 to 10.
In such a semiconductor memory device, when the address signals A3 to A19 which specify the address a are input, a plurality of memory cells corresponding to the address a are selected from the memory cell array 10. The respective information of the memory cells is output from the sense amplifier group 24 as page data.
When the address signals A3 to A19 are changed so as to specify an address b instead of the address a, the address change detector 19 detects the change. Thus, the output .phi.LATCH signal thereof is made active (i.e., "Low") for a short time period. Accordingly, the latch circuit 14 latches the data corresponding to the address a which is specified in the previous access cycle, and outputs the page data to the selector 33. The data selected from the page data at the address a in accordance with the address signals A0 to A2 of the page-mode address is externally output through the output buffer 17.
In general, a semiconductor memory device such as a mask ROM which is generally often used adopts a method in which, when an address (the address a) is input, the data corresponding to the address is output after a time period determined by the access time, and the input of the next address (the address b) is not necessarily required for outputting the data.
However, in the semiconductor memory device having a page mode described in the above-identified publication (Japanese Laid-Open Patent Publication No. 5-144255), it is necessary to input the next address b for reading the data corresponding to the address a. Accordingly, the data at the previous address a cannot be obtained until the next address b is input, so that there exists a time lag, thereby making it difficult to perform the random access operation quickly. Moreover, in the case where the page data corresponding to the last address is to be read, it is necessary to use a dummy cycle in the address signals.
For these reasons, the semiconductor memory device described in the above-identified publication is subjected to serious limitations in practical use, as compared with the general semiconductor memory device.